1. Field of the Invention
The present invention relates to digital data communications and, more specifically, to a system for receiving a data stream that is source synchronous with a received clock.
2. Description of the Prior Art
Most digital circuits employ some sort of clocking circuit to generate a series of clock pulses that activate latches throughout the circuit. When a clock pulse is asserted, a latch is enabled to acquire and store a data value from a logic unit. By asserting clock pulses periodically, data values are able to propagate through the circuit in an orderly manner, thereby ensuring that any given data unit is correctly paired with a corresponding data unit at the beginning of a logical operation.
Some clock signals are received by circuits that employ phase locked loops (PLLs) that sense when a given clock pulse is slightly out of phase with sequential pulses in a clock signal and correct a pulse when such an out of phase relationship is detected. Thus, a slight delay in a received clock pulse will not interfere with the normal timing of operations in a synchronous circuit.
A source synchronous data communications system is one in which a data signal and a corresponding clock signal have been generated from the same original frequency generator and both are transmitted somewhere else. The receiver employs the clock signal to determine when the data on the data signal may be sampled. However, as data transmission speeds increase or the two signal travel through different circuits and for different lengths of transmission media, phase deviations between the clock signal and the data signal develop so that if the receiver relies only on the clock signal, the receiver may not sample data from the data signal at the correct time. These phase deviations may result from several phenomena, including changes in operating temperature, transmission line effects and differences in the frequency response of different circuit elements in the path of the data signal and the clock signal.
To overcome the effect of such phase deviations, some source synchronous systems employ a phase locked loop in which feedback regarding the received data signal is used to adjust the phase of the clock signal to ensure that data sampling occurs at the correct time. Such systems sample the data and provide phase feedback continuously. This is not strictly necessary when the received data is coming from a source synchronous transmitter, nor is it entirely beneficial for certain types of transmitted data patterns. For example, if a data stream includes a long chain of 0's or 1's, the phase locked loop may drift out of lock anyway and start choosing incorrect phase alignments. Also, in cases where short “010” or “101” pattern pulses are runted, i.e., the leading edge of the pulse is late and the trailing edge is early, the runt data patterns can be missed by the receiver completely as the phase locked loop adjustment drifts over time, or the runt pulse can even through the loop out of phase alignment.
Continuously running phase locked loop systems also have the disadvantage of consuming excess power and generating excess heat during steady state operation. This is because once the phase of the clock signal has been aligned with the phase of the data signal in a source synchronous system, the clock signal will normally remain aligned unless some sort of perturbation occurs in the system and, thus, there is no need to continue providing feedback during normal operation. This disadvantage increases in importance as circuit density increases.
Therefore, there is a need for phase locked loop system in which the feedback system operates only during selected periods necessary to align the clock signal with the data signal.